# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2015-2023 Tony Dinh <mibodhi@gmail.com>
#
# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
#
# Boot Media configurations
BOOT_FROM       nand
NAND_ECC_MODE   default
NAND_PAGE_SIZE  0x0800

# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed

# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b

#Dram initalization
DATA 0xFFD01400 0x4301503E      # DDR Configuration register
DATA 0xFFD01404 0xB9843000      # DDR Controller Control Low
DATA 0xFFD01408 0x33137777      # DDR Timing (Low)
DATA 0xFFD0140C 0x16000C55      # DDR Timing (High)
DATA 0xFFD01410 0x04000000      # DDR Address Control
DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
DATA 0xFFD01418 0x00000000	#  DDR Operation
DATA 0xFFD0141C 0x00000672	#  DDR Mode
DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
DATA 0xFFD01424 0x0000F14F	#  DDR Controller Control High
DATA 0xFFD01428 0x000D6720	# DDR3 ODT Read Timing
DATA 0xFFD0147C 0x0000B571	# DDR2 ODT Write Timing
DATA 0xFFD01504 0x1FFFFFF1      # CS[0]n Size
DATA 0xFFD01508 0x20000000      # CS[1]n Base address to 512Mb
DATA 0xFFD0150C 0x1FFFFFF4      # CS[1]n Size 512Mb Window enabled for CS1
DATA 0xFFD01514 0x00000000      # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000      # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00120000      #  DDR ODT Control (Low)
DATA 0xFFD01498 0x00000000      #  DDR ODT Control (High)
DATA 0xFFD0149C 0x0000E803      # CPU ODT Control

DATA 0xFFD015D0 0x00000630
DATA 0xFFD015D4 0x00000046
DATA 0xFFD015D8 0x00000008
DATA 0xFFD015DC 0x00000000
DATA 0xFFD015E0 0x00000023
DATA 0xFFD015E4 0x00203C18
DATA 0xFFD01620 0x00384800
DATA 0xFFD01480 0x00000001
DATA 0xFFD20134 0x66666666
DATA 0xFFD20138 0x00066666

DATA 0xFFD10100 0x00004000	# stop the watchdog
DATA 0xFFD10104 0xFFFFBFFF

# End of Header extension
DATA 0x0 0x0
